Overflow/carry flag in MIPS

I have searched a bit and didn't find anything that properly explained this.

In MIPS you have add and addu to do additions. The main difference is that addu doesn't generate an overflow exceptions.

Let's say we have this binary (I'm using four bits although MIPS is 32 for simplification):

If we add 1 it becomes 1000.

With the add instruction there is an overflow and no carry, since a positive 7 became a negative 1 (assuming two's complement in MIPS). This generates an overflow exception too.

With the addu there is no overflow and no carry, since everything went as expected.

Now let's say you have this binary:

If we add 1 it becomes 0000.

With the add instruction there should be no overflow since a negative 1 became a 0. What about the carry out flag, does it change to 1?

And what happens with the addu instruction? Is it considered overflow, since 15 became 0? I know that there is no overflow exception, but what happens to the overflow flag? Does it get set to 1? What about the carry flag?

asked Nov 11 '18 at 19:12

Myntekt

1501113

1

Which carry flag are you referring to? There's no status register in the MIPS architecture.

– Michael
Nov 12 '18 at 11:18

@Michael oh I thought there was. My bad.

– Myntekt
Nov 13 '18 at 12:18

add a comment |

I have searched a bit and didn't find anything that properly explained this.

In MIPS you have add and addu to do additions. The main difference is that addu doesn't generate an overflow exceptions.

Let's say we have this binary (I'm using four bits although MIPS is 32 for simplification):

If we add 1 it becomes 1000.

With the add instruction there is an overflow and no carry, since a positive 7 became a negative 1 (assuming two's complement in MIPS). This generates an overflow exception too.

With the addu there is no overflow and no carry, since everything went as expected.

Now let's say you have this binary:

If we add 1 it becomes 0000.

With the add instruction there should be no overflow since a negative 1 became a 0. What about the carry out flag, does it change to 1?

asked Nov 11 '18 at 19:12

Myntekt

1501113

1

Which carry flag are you referring to? There's no status register in the MIPS architecture.

– Michael
Nov 12 '18 at 11:18

@Michael oh I thought there was. My bad.

– Myntekt
Nov 13 '18 at 12:18

add a comment |

I have searched a bit and didn't find anything that properly explained this.

In MIPS you have add and addu to do additions. The main difference is that addu doesn't generate an overflow exceptions.

Let's say we have this binary (I'm using four bits although MIPS is 32 for simplification):

If we add 1 it becomes 1000.

With the add instruction there is an overflow and no carry, since a positive 7 became a negative 1 (assuming two's complement in MIPS). This generates an overflow exception too.

With the addu there is no overflow and no carry, since everything went as expected.

Now let's say you have this binary:

If we add 1 it becomes 0000.

With the add instruction there should be no overflow since a negative 1 became a 0. What about the carry out flag, does it change to 1?

asked Nov 11 '18 at 19:12

Myntekt

1501113

I have searched a bit and didn't find anything that properly explained this.

In MIPS you have add and addu to do additions. The main difference is that addu doesn't generate an overflow exceptions.

Let's say we have this binary (I'm using four bits although MIPS is 32 for simplification):

If we add 1 it becomes 1000.

With the add instruction there is an overflow and no carry, since a positive 7 became a negative 1 (assuming two's complement in MIPS). This generates an overflow exception too.

With the addu there is no overflow and no carry, since everything went as expected.

Now let's say you have this binary:

If we add 1 it becomes 0000.

With the add instruction there should be no overflow since a negative 1 became a 0. What about the carry out flag, does it change to 1?

overflow mips carryflag

asked Nov 11 '18 at 19:12

Myntekt

1501113

asked Nov 11 '18 at 19:12

Myntekt

1501113

asked Nov 11 '18 at 19:12

Myntekt

1501113

asked Nov 11 '18 at 19:12

Myntekt

1501113

asked Nov 11 '18 at 19:12

Myntekt

1501113

1

Which carry flag are you referring to? There's no status register in the MIPS architecture.

– Michael
Nov 12 '18 at 11:18

@Michael oh I thought there was. My bad.

– Myntekt
Nov 13 '18 at 12:18

add a comment |

1

Which carry flag are you referring to? There's no status register in the MIPS architecture.

– Michael
Nov 12 '18 at 11:18

@Michael oh I thought there was. My bad.

– Myntekt
Nov 13 '18 at 12:18

Which carry flag are you referring to? There's no status register in the MIPS architecture.

– Michael
Nov 12 '18 at 11:18

@Michael oh I thought there was. My bad.

– Myntekt
Nov 13 '18 at 12:18

add a comment |

1 Answer
1

active

oldest

votes

There is no carryout flag in MIPS architecture.

Overflow exception in the case of addition happens when the sign of the result is different form the expected sign which can happen:

When you add two positive numbers and you get a negative number as a result

When you add two negative numbers and you get a positive number as a result

So yes, in you hypothetical 4 bit MIPS 0111+1 results in an overflow, with the corresponding flag being activated.

edited Nov 19 '18 at 0:37

answered Nov 18 '18 at 17:06

fasiume

236

add a comment |

Your Answer

StackExchange.ifUsing("editor", function ()
StackExchange.using("externalEditor", function ()
StackExchange.using("snippets", function ()
StackExchange.snippets.init();
);
);
, "code-snippets");

StackExchange.ready(function()
var channelOptions =
tags: "".split(" "),
id: "1"
;
initTagRenderer("".split(" "), "".split(" "), channelOptions);

StackExchange.using("externalEditor", function()
// Have to fire editor after snippets, if snippets enabled
if (StackExchange.settings.snippets.snippetsEnabled)
StackExchange.using("snippets", function()
createEditor();
);

else
createEditor();

);

function createEditor()
StackExchange.prepareEditor(
heartbeatType: 'answer',
autoActivateHeartbeat: false,
convertImagesToLinks: true,
noModals: true,
showLowRepImageUploadWarning: true,
reputationToPostImages: 10,
bindNavPrevention: true,
postfix: "",
imageUploader:
brandingHtml: "Powered by u003ca class="icon-imgur-white" href="https://imgur.com/"u003eu003c/au003e",
contentPolicyHtml: "User contributions licensed under u003ca href="https://creativecommons.org/licenses/by-sa/3.0/"u003ecc by-sa 3.0 with attribution requiredu003c/au003e u003ca href="https://stackoverflow.com/legal/content-policy"u003e(content policy)u003c/au003e",
allowUrls: true
,
onDemand: true,
discardSelector: ".discard-answer"
,immediatelyShowMarkdownHelp:true
);

);

draft saved

draft discarded

StackExchange.ready(
function ()
StackExchange.openid.initPostLogin('.new-post-login', 'https%3a%2f%2fstackoverflow.com%2fquestions%2f53252235%2foverflow-carry-flag-in-mips%23new-answer', 'question_page');

);

Post as a guest

Name

Required, but never shown

1 Answer
1

active

oldest

votes

1 Answer
1

active

oldest

votes

There is no carryout flag in MIPS architecture.

Overflow exception in the case of addition happens when the sign of the result is different form the expected sign which can happen:

When you add two positive numbers and you get a negative number as a result

When you add two negative numbers and you get a positive number as a result

So yes, in you hypothetical 4 bit MIPS 0111+1 results in an overflow, with the corresponding flag being activated.

edited Nov 19 '18 at 0:37

answered Nov 18 '18 at 17:06

fasiume

236

add a comment |

There is no carryout flag in MIPS architecture.

Overflow exception in the case of addition happens when the sign of the result is different form the expected sign which can happen:

When you add two positive numbers and you get a negative number as a result

When you add two negative numbers and you get a positive number as a result

So yes, in you hypothetical 4 bit MIPS 0111+1 results in an overflow, with the corresponding flag being activated.

edited Nov 19 '18 at 0:37

answered Nov 18 '18 at 17:06

fasiume

236

add a comment |

There is no carryout flag in MIPS architecture.

Overflow exception in the case of addition happens when the sign of the result is different form the expected sign which can happen:

When you add two positive numbers and you get a negative number as a result

When you add two negative numbers and you get a positive number as a result

So yes, in you hypothetical 4 bit MIPS 0111+1 results in an overflow, with the corresponding flag being activated.

edited Nov 19 '18 at 0:37

answered Nov 18 '18 at 17:06

fasiume

236

There is no carryout flag in MIPS architecture.

Overflow exception in the case of addition happens when the sign of the result is different form the expected sign which can happen:

When you add two positive numbers and you get a negative number as a result

When you add two negative numbers and you get a positive number as a result

So yes, in you hypothetical 4 bit MIPS 0111+1 results in an overflow, with the corresponding flag being activated.

edited Nov 19 '18 at 0:37

answered Nov 18 '18 at 17:06

fasiume

236

edited Nov 19 '18 at 0:37

answered Nov 18 '18 at 17:06

fasiume

236

answered Nov 18 '18 at 17:06

fasiume

236

answered Nov 18 '18 at 17:06

fasiume

236

add a comment |

draft saved

draft discarded

Thanks for contributing an answer to Stack Overflow!

Please be sure to answer the question. Provide details and share your research!

But avoid …

Asking for help, clarification, or responding to other answers.

Making statements based on opinion; back them up with references or personal experience.

To learn more, see our tips on writing great answers.

draft saved

draft discarded

Post as a guest

Name

Required, but never shown

Name

Required, but never shown

Name

Required, but never shown

This page is only for reference, If you need detailed information, please check here

搜尋此網誌

Dfyjkt