Large SiGe ASICs for digital logic
$begingroup$
I am trying to understand if digital ASICs with tens of millions of silicon-germanium gates exist. A comment in another post states (emphasis mine) "SiGe can hit 5 GHz pretty easily even with half a billion gates"—I am trying to confirm or refute this statement.
Below is how I understand things. SiGe (for example, SiGe 9HP from Global Foundries) is a BiCMOS process which integrates two separate technologies. It contains a "cost-effective mature silicon base" which is the 90 nm Si process. On top of this base, it allows for the use of SiGe NPN transistors with "exceptional high-frequency performance".
Looking at the applications of the SiGe 9HP process, it seems these NPN transistors are used for analogue purposes, e.g. for LIDAR, RADAR, 5G, Ethernet, etc. I have not found applications using NPN transistors to build large scale digital logic. A leading SiGe researcher has a list of "selected SiGe circuits" (see right column) and none seems to be large scale digital circuits.
As a side note, I found SiGe used in the context of strained silicon, but as I understand strained silicon is just Si CMOS.
My questions regarding the SiGe process are:
- Are SiGe NPN transistors used to build digital gates?
- Can digital ASICs be built from tens of millions of SiGe gates?
- If the answer to 2) is "yes", are there public examples?
- If the answer of 2) is "no", why not (e.g. size, power, yield, ...)?
transistors semiconductors asic
edited Aug 26 '18 at 17:11
Peter Mortensen
1,60031422
asked Aug 26 '18 at 9:49
RandomblueRandomblue
4,4202380152
$endgroup$
add a comment |
$begingroup$
I am trying to understand if digital ASICs with tens of millions of silicon-germanium gates exist. A comment in another post states (emphasis mine) "SiGe can hit 5 GHz pretty easily even with half a billion gates"—I am trying to confirm or refute this statement.
Below is how I understand things. SiGe (for example, SiGe 9HP from Global Foundries) is a BiCMOS process which integrates two separate technologies. It contains a "cost-effective mature silicon base" which is the 90 nm Si process. On top of this base, it allows for the use of SiGe NPN transistors with "exceptional high-frequency performance".
Looking at the applications of the SiGe 9HP process, it seems these NPN transistors are used for analogue purposes, e.g. for LIDAR, RADAR, 5G, Ethernet, etc. I have not found applications using NPN transistors to build large scale digital logic. A leading SiGe researcher has a list of "selected SiGe circuits" (see right column) and none seems to be large scale digital circuits.
As a side note, I found SiGe used in the context of strained silicon, but as I understand strained silicon is just Si CMOS.
My questions regarding the SiGe process are:
- Are SiGe NPN transistors used to build digital gates?
- Can digital ASICs be built from tens of millions of SiGe gates?
- If the answer to 2) is "yes", are there public examples?
- If the answer of 2) is "no", why not (e.g. size, power, yield, ...)?
transistors semiconductors asic
edited Aug 26 '18 at 17:11
Peter Mortensen
1,60031422
asked Aug 26 '18 at 9:49
RandomblueRandomblue
4,4202380152
$endgroup$
1
$begingroup$
I share your concern – you'd typically MOS in digital logic to avoid humongous static currents.
$endgroup$
– Marcus Müller
Aug 26 '18 at 9:54
$begingroup$
Do you know the (ballpark) static current of a SiGe NPN transistor?
$endgroup$
– Randomblue
Aug 26 '18 at 10:05
2
$begingroup$
You mean quiescent or biasing current which is needed to make CML (Current mode logic) work. I think I had to use in the order of a couple of mA per logic gate to make it operate at 40 GHz for example. That's in GlobalFoundries 8HP process btw but that will not scale down much in a newer process because parasitics introduced by wiring etc stay roughly the same. I think the limit (for speed) is the maximum current density allowed in the transistors. Depending on the transistor that limit is in the order of 10 to 100 mA per transistor.
$endgroup$
– Bimpelrekkie
Aug 26 '18 at 10:33
add a comment |
$begingroup$
I am trying to understand if digital ASICs with tens of millions of silicon-germanium gates exist. A comment in another post states (emphasis mine) "SiGe can hit 5 GHz pretty easily even with half a billion gates"—I am trying to confirm or refute this statement.
Below is how I understand things. SiGe (for example, SiGe 9HP from Global Foundries) is a BiCMOS process which integrates two separate technologies. It contains a "cost-effective mature silicon base" which is the 90 nm Si process. On top of this base, it allows for the use of SiGe NPN transistors with "exceptional high-frequency performance".
Looking at the applications of the SiGe 9HP process, it seems these NPN transistors are used for analogue purposes, e.g. for LIDAR, RADAR, 5G, Ethernet, etc. I have not found applications using NPN transistors to build large scale digital logic. A leading SiGe researcher has a list of "selected SiGe circuits" (see right column) and none seems to be large scale digital circuits.
As a side note, I found SiGe used in the context of strained silicon, but as I understand strained silicon is just Si CMOS.
My questions regarding the SiGe process are:
- Are SiGe NPN transistors used to build digital gates?
- Can digital ASICs be built from tens of millions of SiGe gates?
- If the answer to 2) is "yes", are there public examples?
- If the answer of 2) is "no", why not (e.g. size, power, yield, ...)?
transistors semiconductors asic
edited Aug 26 '18 at 17:11
Peter Mortensen
1,60031422
asked Aug 26 '18 at 9:49
RandomblueRandomblue
4,4202380152
$endgroup$
I am trying to understand if digital ASICs with tens of millions of silicon-germanium gates exist. A comment in another post states (emphasis mine) "SiGe can hit 5 GHz pretty easily even with half a billion gates"—I am trying to confirm or refute this statement.
Below is how I understand things. SiGe (for example, SiGe 9HP from Global Foundries) is a BiCMOS process which integrates two separate technologies. It contains a "cost-effective mature silicon base" which is the 90 nm Si process. On top of this base, it allows for the use of SiGe NPN transistors with "exceptional high-frequency performance".
Looking at the applications of the SiGe 9HP process, it seems these NPN transistors are used for analogue purposes, e.g. for LIDAR, RADAR, 5G, Ethernet, etc. I have not found applications using NPN transistors to build large scale digital logic. A leading SiGe researcher has a list of "selected SiGe circuits" (see right column) and none seems to be large scale digital circuits.
As a side note, I found SiGe used in the context of strained silicon, but as I understand strained silicon is just Si CMOS.
My questions regarding the SiGe process are:
- Are SiGe NPN transistors used to build digital gates?
- Can digital ASICs be built from tens of millions of SiGe gates?
- If the answer to 2) is "yes", are there public examples?
- If the answer of 2) is "no", why not (e.g. size, power, yield, ...)?
transistors semiconductors asic
transistors semiconductors asic
edited Aug 26 '18 at 17:11
Peter Mortensen
1,60031422
asked Aug 26 '18 at 9:49
RandomblueRandomblue
4,4202380152
edited Aug 26 '18 at 17:11
Peter Mortensen
1,60031422
asked Aug 26 '18 at 9:49
RandomblueRandomblue
4,4202380152
edited Aug 26 '18 at 17:11
Peter Mortensen
1,60031422
edited Aug 26 '18 at 17:11
Peter Mortensen
1,60031422
edited Aug 26 '18 at 17:11
Peter Mortensen
1,60031422
1,60031422
asked Aug 26 '18 at 9:49
RandomblueRandomblue
4,4202380152
asked Aug 26 '18 at 9:49
RandomblueRandomblue
4,4202380152
asked Aug 26 '18 at 9:49
RandomblueRandomblue
4,4202380152
4,4202380152
1
$begingroup$
I share your concern – you'd typically MOS in digital logic to avoid humongous static currents.
$endgroup$
– Marcus Müller
Aug 26 '18 at 9:54
$begingroup$
Do you know the (ballpark) static current of a SiGe NPN transistor?
$endgroup$
– Randomblue
Aug 26 '18 at 10:05
2
$begingroup$
You mean quiescent or biasing current which is needed to make CML (Current mode logic) work. I think I had to use in the order of a couple of mA per logic gate to make it operate at 40 GHz for example. That's in GlobalFoundries 8HP process btw but that will not scale down much in a newer process because parasitics introduced by wiring etc stay roughly the same. I think the limit (for speed) is the maximum current density allowed in the transistors. Depending on the transistor that limit is in the order of 10 to 100 mA per transistor.
$endgroup$
– Bimpelrekkie
Aug 26 '18 at 10:33
add a comment |
1
$begingroup$
I share your concern – you'd typically MOS in digital logic to avoid humongous static currents.
$endgroup$
– Marcus Müller
Aug 26 '18 at 9:54
$begingroup$
Do you know the (ballpark) static current of a SiGe NPN transistor?
$endgroup$
– Randomblue
Aug 26 '18 at 10:05
2
$begingroup$
You mean quiescent or biasing current which is needed to make CML (Current mode logic) work. I think I had to use in the order of a couple of mA per logic gate to make it operate at 40 GHz for example. That's in GlobalFoundries 8HP process btw but that will not scale down much in a newer process because parasitics introduced by wiring etc stay roughly the same. I think the limit (for speed) is the maximum current density allowed in the transistors. Depending on the transistor that limit is in the order of 10 to 100 mA per transistor.
$endgroup$
– Bimpelrekkie
Aug 26 '18 at 10:33
1
1
$begingroup$
I share your concern – you'd typically MOS in digital logic to avoid humongous static currents.
$endgroup$
– Marcus Müller
Aug 26 '18 at 9:54
$begingroup$
I share your concern – you'd typically MOS in digital logic to avoid humongous static currents.
$endgroup$
– Marcus Müller
Aug 26 '18 at 9:54
$begingroup$
Do you know the (ballpark) static current of a SiGe NPN transistor?
$endgroup$
– Randomblue
Aug 26 '18 at 10:05
$begingroup$
Do you know the (ballpark) static current of a SiGe NPN transistor?
$endgroup$
– Randomblue
Aug 26 '18 at 10:05
2
2
$begingroup$
You mean quiescent or biasing current which is needed to make CML (Current mode logic) work. I think I had to use in the order of a couple of mA per logic gate to make it operate at 40 GHz for example. That's in GlobalFoundries 8HP process btw but that will not scale down much in a newer process because parasitics introduced by wiring etc stay roughly the same. I think the limit (for speed) is the maximum current density allowed in the transistors. Depending on the transistor that limit is in the order of 10 to 100 mA per transistor.
$endgroup$
– Bimpelrekkie
Aug 26 '18 at 10:33
$begingroup$
You mean quiescent or biasing current which is needed to make CML (Current mode logic) work. I think I had to use in the order of a couple of mA per logic gate to make it operate at 40 GHz for example. That's in GlobalFoundries 8HP process btw but that will not scale down much in a newer process because parasitics introduced by wiring etc stay roughly the same. I think the limit (for speed) is the maximum current density allowed in the transistors. Depending on the transistor that limit is in the order of 10 to 100 mA per transistor.
$endgroup$
– Bimpelrekkie
Aug 26 '18 at 10:33
add a comment |
1 Answer
1
active
oldest
votes
$begingroup$
NPN and PNP transistors use more current when building logic. You need to pass current through the base-emitter junction in order to turn them on. In MOS, to first order, the only current you need is to charge the gate capacitance.
This is why CMOS has replaced bipolar in almost all logic applications (there are exceptions, such as ECL in PLL dividers).
So to answer your questions:
Are SiGe NPN transistors used to build digital gates?
Yes. This is done either for very simple, small logic, when you might need a few hundred control gates in a power amplifier or similar (and you can save the cost of the BiCMOS part in the process), or when logic needs to be really fast (for example in some of the building blocks in PLLs).
Can digital ASICs be built from tens of millions of SiGe gates?
While I don't think there is a physical reason why not, the current required to power such a chip makes it practically unfeasible - it would get very hot and expensive. The advantages of CMOS just make it to be an excellent digital technology.
answered Aug 26 '18 at 10:05
Joren VaesJoren Vaes
8,1561545
$endgroup$
$begingroup$
Do you have figures regarding the current requirements of a SiGe NPN transistor?
$endgroup$
– Randomblue
Aug 26 '18 at 10:07
add a comment |
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$begingroup$
NPN and PNP transistors use more current when building logic. You need to pass current through the base-emitter junction in order to turn them on. In MOS, to first order, the only current you need is to charge the gate capacitance.
This is why CMOS has replaced bipolar in almost all logic applications (there are exceptions, such as ECL in PLL dividers).
So to answer your questions:
Are SiGe NPN transistors used to build digital gates?
Yes. This is done either for very simple, small logic, when you might need a few hundred control gates in a power amplifier or similar (and you can save the cost of the BiCMOS part in the process), or when logic needs to be really fast (for example in some of the building blocks in PLLs).
Can digital ASICs be built from tens of millions of SiGe gates?
While I don't think there is a physical reason why not, the current required to power such a chip makes it practically unfeasible - it would get very hot and expensive. The advantages of CMOS just make it to be an excellent digital technology.
answered Aug 26 '18 at 10:05
Joren VaesJoren Vaes
8,1561545
$endgroup$
$begingroup$
Do you have figures regarding the current requirements of a SiGe NPN transistor?
$endgroup$
– Randomblue
Aug 26 '18 at 10:07
add a comment |
$begingroup$
NPN and PNP transistors use more current when building logic. You need to pass current through the base-emitter junction in order to turn them on. In MOS, to first order, the only current you need is to charge the gate capacitance.
This is why CMOS has replaced bipolar in almost all logic applications (there are exceptions, such as ECL in PLL dividers).
So to answer your questions:
Are SiGe NPN transistors used to build digital gates?
Yes. This is done either for very simple, small logic, when you might need a few hundred control gates in a power amplifier or similar (and you can save the cost of the BiCMOS part in the process), or when logic needs to be really fast (for example in some of the building blocks in PLLs).
Can digital ASICs be built from tens of millions of SiGe gates?
While I don't think there is a physical reason why not, the current required to power such a chip makes it practically unfeasible - it would get very hot and expensive. The advantages of CMOS just make it to be an excellent digital technology.
answered Aug 26 '18 at 10:05
Joren VaesJoren Vaes
8,1561545
$endgroup$
$begingroup$
Do you have figures regarding the current requirements of a SiGe NPN transistor?
$endgroup$
– Randomblue
Aug 26 '18 at 10:07
add a comment |
$begingroup$
NPN and PNP transistors use more current when building logic. You need to pass current through the base-emitter junction in order to turn them on. In MOS, to first order, the only current you need is to charge the gate capacitance.
This is why CMOS has replaced bipolar in almost all logic applications (there are exceptions, such as ECL in PLL dividers).
So to answer your questions:
Are SiGe NPN transistors used to build digital gates?
Yes. This is done either for very simple, small logic, when you might need a few hundred control gates in a power amplifier or similar (and you can save the cost of the BiCMOS part in the process), or when logic needs to be really fast (for example in some of the building blocks in PLLs).
Can digital ASICs be built from tens of millions of SiGe gates?
While I don't think there is a physical reason why not, the current required to power such a chip makes it practically unfeasible - it would get very hot and expensive. The advantages of CMOS just make it to be an excellent digital technology.
answered Aug 26 '18 at 10:05
Joren VaesJoren Vaes
8,1561545
$endgroup$
NPN and PNP transistors use more current when building logic. You need to pass current through the base-emitter junction in order to turn them on. In MOS, to first order, the only current you need is to charge the gate capacitance.
This is why CMOS has replaced bipolar in almost all logic applications (there are exceptions, such as ECL in PLL dividers).
So to answer your questions:
Are SiGe NPN transistors used to build digital gates?
Yes. This is done either for very simple, small logic, when you might need a few hundred control gates in a power amplifier or similar (and you can save the cost of the BiCMOS part in the process), or when logic needs to be really fast (for example in some of the building blocks in PLLs).
Can digital ASICs be built from tens of millions of SiGe gates?
While I don't think there is a physical reason why not, the current required to power such a chip makes it practically unfeasible - it would get very hot and expensive. The advantages of CMOS just make it to be an excellent digital technology.
answered Aug 26 '18 at 10:05
Joren VaesJoren Vaes
8,1561545
answered Aug 26 '18 at 10:05
Joren VaesJoren Vaes
8,1561545
answered Aug 26 '18 at 10:05
Joren VaesJoren Vaes
8,1561545
answered Aug 26 '18 at 10:05
Joren VaesJoren Vaes
8,1561545
8,1561545
$begingroup$
Do you have figures regarding the current requirements of a SiGe NPN transistor?
$endgroup$
– Randomblue
Aug 26 '18 at 10:07
add a comment |
$begingroup$
Do you have figures regarding the current requirements of a SiGe NPN transistor?
$endgroup$
– Randomblue
Aug 26 '18 at 10:07
$begingroup$
Do you have figures regarding the current requirements of a SiGe NPN transistor?
$endgroup$
– Randomblue
Aug 26 '18 at 10:07
$begingroup$
Do you have figures regarding the current requirements of a SiGe NPN transistor?
$endgroup$
– Randomblue
Aug 26 '18 at 10:07
add a comment |
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1
$begingroup$
I share your concern – you'd typically MOS in digital logic to avoid humongous static currents.
$endgroup$
– Marcus Müller
Aug 26 '18 at 9:54
$begingroup$
Do you know the (ballpark) static current of a SiGe NPN transistor?
$endgroup$
– Randomblue
Aug 26 '18 at 10:05
2
$begingroup$
You mean quiescent or biasing current which is needed to make CML (Current mode logic) work. I think I had to use in the order of a couple of mA per logic gate to make it operate at 40 GHz for example. That's in GlobalFoundries 8HP process btw but that will not scale down much in a newer process because parasitics introduced by wiring etc stay roughly the same. I think the limit (for speed) is the maximum current density allowed in the transistors. Depending on the transistor that limit is in the order of 10 to 100 mA per transistor.
$endgroup$
– Bimpelrekkie
Aug 26 '18 at 10:33